The RelChipTM RC2110836 is a synchronous 8Kx36 SRAM compatible with the RC10001 microcontroller. The part supports a 32-bit address/data multiplexed bus. Word (32-bit), halfword (16-bit) and byte operations are supported. Every byte has associated parity or 9th data bit of storage.
The memory is highly configurable, with options for data width, parity, latency, and burst-mode. Each byte of the basic thirty-two data pins can be written individually with the byte write (BW0n through BW3n) control pins.
Parity, latency, and burst-mode are configurable through read/write registers. The memory is physically 36 bits wide to accommodate parity and the 9th data bit. The part can also be used as 32 bits wide.
The ninth data bit/parity bit can be set to unused, 9th data bit, or parity. Parity options include none, even, odd, sticky, and parity error. The parity is calculated during a write and reported during a read. If the parity error mode is selected, this is checked during a read.
Latency can be set from one to eight cycles, and applies to the first read or write data cycle. In burst mode, four consecutive operations are performed per address cycle.