The RC2103209 is a synchronous 32Kx9 SRAM. The part uses a multiplexed bus (address and data). Ninth bit or parity is selected by pin configuration.
Fifteen bits of address are provided during the address cycle. Eight bits of data plus parity are transferred in the data cycle.
The ninth data bit (on the PDQ pin) is configured for data or parity by the PAR0 through PAR2 pins. These pins should all be tied to power or ground. The options are no connect, 9th data bit, even parity, odd parity, sticky parity, or parity error. Parity is stored in memory during a write, and checked during a read.